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NCP5209 Product Preview 4-In-1 PWM Buck and Tri-Linear DDR Power Controller
The NCP5209 4-In-1 PWM Buck and Tri-Linear Power Controller is a complete ACPI compliant power solution for MCH and DDR memory. This IC combines the high efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulator for the VTT termination voltage as well as the MCH core supply voltage. This IC contains a synchronous PWM buck controller for driving two external NFETs to form the DDR memory supply voltage (VDDQ). The DDR memory termination regulator (VTT) is designed to track at the half of reference voltage while sourcing and sinking current. The two linear regulator controllers driving two external NFETs are cascaded to produce the MCH core voltage (VMCH). Protective features include, soft-start circuitry, under-voltage monitoring of 5VDUAL, 5VATX and 12VATX, and thermal shutdown. The IC is packaged in a QFN-20.
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18
1 20-LEAD QFN MN SUFFIX CASE 505
NCP5209 AWLYYWW 1
* Synchronous PWM Buck Controller for VDDQ * Integrated Power FETs with VTT Regulator Sourcing/Sinking up to * * * * * * * * * * * *
1.8 A Two Linear Regulator Drivers for VMCH All External Power MOSFETs are N-Channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage or can be Adjusted Externally Fixed Switching Frequency of 250 kHz for DDQ Regulator in Normal Mode Doubled switching frequency (500 kHz) for DDQ Regulator in Standby Mode Soft-Start Protection for all Regulators Under-V oltage Monitoring of Supply Voltages Over-Current Protection for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Protects against Reverse DIMM Insertion Thermal Shutdown Housed in QFN-20
NCP5209 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
PIN CONNECTIONS
COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 SW_DDQ BG_DDQ TG_TDQ BOOT 5VDUAL OCDDQ BUF_Cut DRV_2P4 FB2P4 DRV_1P5
Applications
* DDR I and DDR II Memory and MCH Power Supply
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
ORDERING INFORMATION
Device NCP5209MN Package 20-Lead QFN* Shipping Rail Tape and Reel
NCP5209MNR2 20-Lead QFN* *5 x 6 mm
(c) Semiconductor Components Industries, LLC, 2003
1
September, 2003 - Rev. P0
Publication Order Number: NCP5209/D
NCP5209
CL1 5VATX BUF_Cut BUF_Cut SS CSS OCDDQ BOOT SCHOTTKY RL1 SCHOTTKY 12VATX
13 V Zener
1.25 V, 1.8 Apk COUT2
VTT R3
VTT
5VDUAL 5VDUAL
FBVTT R4 TGDDQ REF_SNS M1 L AGND 3.3VATX M3 DRV_2P4 VDDQ 2.5 V, 20 A COUT1 M2
DDQ_REF
NCP5209
SWDDQ BGDDQ PGND COMP_DDQ
2P4V COUT3
R5
FB2P4 CZ1 R6 FBDDQ RZ1
CZ2 R1
CP1
RZ2
M4 1P5V R7 1.5 V, 7 A COUT4 R8
DRV_1P5
R2
FB1P5 VDDQ
Figure 1. Application Diagram
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VREF1 VOLTAGE and CURRENT REFERENCE BUF_CUT BOOT R10 + - _INREGDDQ 5VDUAL- UVLO 5VDLGD ILIM + - IREF BOOT TGDDQ M1 VDDQ L 5VATX- UVLO _5VDLGD VDDQ PWM LOGIC PGND BOOT SDDQ RSWDDQ BGDDQ PGND COMP_DDQ VREF1 AMP + - + A1 - FBDDQ R2 CZ2 CZ1 RZ1 CP1 RZ2 R1 M2 COUT1 5VDUAL BOOT- UVLO _BOOTGD CONTROL LOGIC S0 S3 BOOT Schottky 13 V Zener Schottky VREF2 _VREFQD TSD THERMAL SHUTDOWN OCDDQ BOOT 12VATX CL1 RL1 5VATX
VREF1 R11 5VDUAL R12
5VDUAL
+ VREF1 R13 - OCDDQ R14 + VREF1 - R15 SS OSC CSS
PGND S0 S3
DDQ_REF S0 R16 VTT Regulation Control R17 R18 - R19 + AGND PGND 5VDUAL BOOT + - R5 AGND S0 VREF2 5VDUAL BOOT + - PGND AGND FB1P5 AGND R8 COUT4 DRV_IP5 R7 1P5V PGND FB2P4 R6 M4 COUT3 DRV_2P4 M3 2P4V M3 R4 FBVTT 5VDUAL - + VTT AGND 5VDUAL VTT R3 COUT2 M2 VDDQ
VREF2
Figure 2. Internal Block Diagram.
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PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol COMP FBDDQ SS PGND VTT VDDQ AGND FBVTT DDQ_REF FB1P5 DRV_1P5 FB2P4 DRV_2P4 BUF_CUT OCDDQ 5VDUAL BOOT TGDDQ BGDDQ SWDDQ VDDQ Error Amplifier Compensation Node. VDDQ Regulator Feedback Pin for Closed Loop Regulation. Soft Start Capacitor Connection to Ground. Power Ground VTT Regulator Output Power Input for VTT Linear Regulator Analog Ground Connection and Remote Ground Sense. VTT Linear Regulator Feedback pin for Closed Loop Regulation. VDDQ Reference Voltage Input of VTT Regulator. 2nd Linear Regulator Feedback Pin for Closed Loop Regulation. 2nd Linear Regulator Gate Driver Output for N-Channel Power FET. 1st Linear Regulator Feedback Pin for Closed Loop Regulation. 1st Linear Regulator Gate Driver Output for N-Channel Power FET. Active High Control Signal to Activate S3 Sleep State. Over-current Sense and Program Input for the VDDQ High Side FET. 5 V Dual Supply Input Gate Driver Input Supply. A Boost Capacitor is Connected between SWDDQ and BOOT. Gate Driver Output for VDDQ Regulator High Side N-Channel Power FET. Gate Driver Output for VDDQ Regulator Low Side N-Channel Power FET. DDQ Regulator Current Limit Sense Input. A Protection Resistor Should be Connected between the Inductor Driven Node and SWDDQ. Descriptions
MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 16) to AGND (Pin 7) Gate Drive Voltage (Pin 11, 13, 17-19) to AGND (PIN 7) Input / Output Pins to AGND (Pin 7) Pin 1-6, 8-10, 12, 14-15, 20 Thermal Characteristics QFN-20 Plastic Package Thermal Resistance Junction-to-Air Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115. 2. Latch-up Current Maximum Rating: 150 mA per JEDEC standard: JESD78. Symbol 5VDUAL VCC, Vg VIO RqJA_Q Value -0.3, 6.0 -0.3, 14 -0.3, 6.0 68 Unit V V V C/W
TJ TA Tstg MSL
0 to + 150 0 to + 70 - 55 to +150
C C C
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(5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0 to 70C, L = 1.7 mH, COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = 680 mF, COUT4 = 3300 mF, CSS = 33 nF, RL1 = 50 kW, R1 = 2.2 kW, R2 = 2 kW, R3 = 0 W, R4 = 1 kW, R5 = 10 kW, R6 = 5 kW, R7 = 6.8 W, R8 = 7.5 kW, RSWDDQ = 1 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.) Characteristic SUPPLY VOLTAGE 5VDUAL Operating Voltage OCDDQ Operating Voltage BOOT Operating Voltage Supply Current S0 mode Supply Current from 5VDUAL S3 mode Supply Current from 5VDUAL S5 mode Supply Current from 5VDUAL S0 mode Supply Current from BOOT BUF_CUT = LOW, BOOT = 12 V, 5VATX = 5 V BUF_CUT = HIGH, 5VATX = 0 V BUF_CUT = LOW, 5VATX = 0 V BUF_CUT = LOW, BOOT=12 V, 5VATX = 5 V, TGDDQ, BGDDQ, DRV_2P4 and DRV_1P5 Open BUF_CUT = HIGH, 5VATX=0 V, TGDDQ, BGDDQ, DRV_2P4 and DRV_1P5 Open I5VDL_S0 I5VDL_S3 I5VDL_S5 IBOOT_S0 7 5 1 40 mA mA mA mA V5VDUAL VOCDDQ VBOOT 4.5 4.5 5.0 5.0 12.0 5.5 5.5 13.2 V V V Test Conditions Symbol Min Typ Max Unit
ELECTRICAL CHARACTERISTICS
S3 mode Supply Current from BOOT
IBOOT_S3
10
mA
Under-Voltage-Monitor 5VDUAL UVLO Upper Threshold 5VDUAL UVLO Hysteresis BOOT UVLO Upper Threshold BOOT UVLO Hysteresis OCDDQ UVLO Upper Threshold OCDDQ UVLO Hysteresis Thermal Shutdown Thermal Shutdown Thermal Shutdown Hysteresis DDQ Switching Regulator FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency in S0 Mode Oscillator Frequency in S3 Mode OCDDQ pin Current Sink Current Limit Blanking Time in S0 Mode Minimum Duty Cycle in S0 Mode Maximum Duty Cycle in S0 Mode DDQ Switching Regulator Minimum Duty Cycle in S3 Mode Maximum Duty Cycle in S3 Mode Soft-Start Timing DDQ ERROR AMPLIFIER DC Gain GAINDDQ 70 dB DS3min DS3max Tss1 10 0 90 % % ms V(OCDDQ) = 3 V TA = 25C TA = 0 to 70C V(FBDDQ) = 1.190 V VFBQ IDDQfb FDDQS0 FDDQS3 IOCDDQ TDDQbk DS0min DS0max 225 450 28 400 0 100 250 500 40 1.178 1.166 1.190 1.190 1.202 1.214 1 275 550 52 V mA kHz kHz mA ns % % Tsd Tsdhys 140 25 C C V5VDLUV+ V5VDLhys VBOOTUV+ VBOOThys OCDDQUV+ OCDDQhys 200 1.0 1.25 300 10.2 4.4 V mV V V V mV
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(5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0 to 70C, L = 1.7 mH, COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = 680 mF, COUT4 = 3300 mF, CSS = 33 nF, RL1 = 50 kW, R1 = 2.2 kW, R2 = 2 kW, R3 = 0 W, R4 = 1 kW, R5 = 10 kW, R6 = 5 kW, R7 = 6.8 W, R8 = 7.5 kW, RSWDDQ = 1 kW, RZ1 = 20 kW, RZ2 = 8 W, CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.) Characteristic DDQ ERROR AMPLIFIER Gain-Bandwidth Product Slew Rate VTT Active Termination Regulator VTT tracking REF_SNS/2 at S0 mode VTT Source Current Limit VTT Sink Current Limit DDQ_REF Input Resistance Dual Linear Regulator Controller 1st Regulator Feedback Voltage, Control Loop in Regulation 1st Regulator Feedback Input Current 1st Regulator DC Gain 2nd Regulator Feedback Voltage, Control Loop in Regulation 2nd Regulator Feedback Input Current 2nd Regulator DC Gain Internal Soft-Start Timing Control Section BUF_CUT Input Logic HIGH BUF_CUT Input Logic LOW BUF_CUT Input Current Gate Drivers TGDDQ Gate Pull-HIGH Resistance TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance DRV_2P4 Gate Pull-HIGH Voltage DRV_2P4 Gate Pull-LOW Voltage DRV_2P4 Gate Source Current DRV_2P4 Gate Sink Current DRV_1P5 Gate Pull-HIGH Voltage DRV_1P5 Gate Pull-LOW Voltage DRV_1P5 Gate Source Current DRV_1P5 Gate Sink Current BOOT = 12 V, V(TGDDQ) = 11.9 V BOOT = 12 V, V(TGDDQ) = 0.1 V BOOT = 12 V, V(BGDDQ) = 11.9 V BOOT = 12 V, V(BGDDQ) = 0.1 V BOOT = 12 V BOOT = 12 V BOOT = 12 V BOOT = 12 V BOOT = 12 V BOOT = 12 V BOOT = 12 V BOOT = 12 V RH_TG RL_TG RH_BG RL_BG VH2P4 VL2P4 IH2P4 IL2P4 VH1P5 VL1P5 IH1P5 IL1P5 3.5 2.5 3.5 1.3 9.0 0.8 10 10 9.0 0.8 10 10 W W W W V V mA mA V V mA mA Logic_H Logic_L ILogic 2.0 0.8 1 V V mA TA = 0C to 70C TA = 0C to 70C VFB2P4 IFB2P4 GAIN2P4 VFB1P5 IFB1P5 GAIN1P5 Tss2 66 1.5 0.784 66 0.800 0.816 1 0.784 0.800 0.816 1 V mA dB V mA dB ms IOUT= 0 to 1.8 A (Sink Current) IOUT= 0 to -1.8 A (Source Current) adVTTS0 ILIMVTsrc ILIMVTsnk RDDQ_REF -30 2.4 2.4 50 30 mV A A W COMP_DDQ = 220 nF, 1 W in Series COMP_DDQ = 10 pF GBWDDQ SRDDQ TBD 8 MHz V/ms Test Conditions Symbol Min Typ Max Unit
ELECTRICAL CHARACTERISTICS
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DETAILED OPERATION DESCRIPTIONS
General
The NCP5209 4-In-1 PWM Buck and Tri-Linear DDR Power Controller contains a high efficiency PWM controller, an integrated two-quadrant linear regulator and two linear regulator controllers. The VDDQ supply is generated by a PWM controller driving two external NFETs. The VTT termination voltage is tracked by an integrated linear regulator with sourcing and sinking current capability. The dual linear controllers driving two external NFETs can either be cascaded to create the MCH core voltage or work independently to produced two regulated output voltages. All regulator outputs are adjustable. The inclusion of soft-start, supply under-voltage monitors, over-current protection and thermal shutdown, makes this device a complete power solution for the MCH and DDR memory system. This device is packaged in QFN-20.
ACPI Control Logic
S0 normal operating mode, in which, all regulators are running. The transition of BUF_CUT from LOW to HIGH in S0 mode triggers the device into the S3 sleep mode. In S3 mode, the external 12VATX and 5VATX supplies collapse and only the VDDQ regulator is working. During S3 mode, the transition of BUF_CUT from HIGH to LOW triggers the device back to S0 mode providing 12ATX and 5VATX are good. The IC can re-enter S5 mode from S0 mode by removing one of the supplies. Transitions from S3 to S5 or vice versa are not allowed. A timing diagram is shown in Figure 4. Table 1 summarizes the operating states of all regulators and the conditions of the output pins.
S5-To-S0 Mode Power Up Sequence
The ACPI control logic is powered by the 5VDUAL supply input. The BUF_CUT input and the three supply voltage monitoring signals from the internal UVLOs are used to decode the operating mode in accordance with the state transition diagram shown in Figure 5. The 5VDUAL supply must come up before the other supplies. The UVLOs monitor the motherboard supplies 5VDUAL, 12VATX and 5VATX through the 5VDUAL, BOOT and OCDDQ pins respectively. Three control signals, _5VDUALGD, _BOOTGD and _OCDDQGD, are asserted when the supply voltages are in good condition. When the device is first powered up, it is in S5 shutdown mode to minimize the power consumption. When all three supplies are good and BUF_CUT is LOW the device enters
Table 1. Mode, Operation and Output Pin Condition
OPERATING CONDITIONS MODE S0 S3 S5 DDQ Normal Standby H-Z VTT Normal H-Z H-Z Dual Linear Normal H-Z H-Z
An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD is asserted to wake up the ACPI logic. The assertion of VREFGD enables the ACPI control logic. Once the ACPI control is activated, the power up sequence starts by waking up the 5VDUAL voltage monitor block and reference current generator first. After 5VDUAL is within the preset level, the BOOT and OCDDQ under voltage monitor blocks are enabled to detect the presence of the 12VATX and 5VATX supplies. When the three supplies are in regulation and BUFCUT is LOW the device enters S0 mode by activating the soft-start of VDDQ switching regulator. After the VDDQ regulator is in regulation and the soft-start interval is completed, the _INREGDDQ signal is asserted to wake up the VTT regulator and the dual linear controllers.
OUTPUT PIN CONDITIONS TGDDQ Normal Standby Low BGDDQ Normal Standby Low DRV_2P4 Normal Low Low DRV_1P5 Normal Low Low
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VDDQ Switching Regulator
The VDDQ regulator in S0 mode is a synchronous buck controller that drives two external power NFETs to supply up to 25 A. It employs the voltage mode fixed frequency PWM control scheme with external compensation switching at 250 kHz 10%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ x (1 + R2/R1). This amplifier compares the feedback voltage with an internal VREF1 (=1.190 V) to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform to generate a PWM signal. This PWM signal drives the external NFETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output voltage. When the NCP5209 leaves S5 mode, the VDDQ output voltage ramps up at a rate controlled by the capacitor at the SS pin. When VDDQ is regulating in S0 mode, a signal _INREGDDQ goes HIGH. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external NFETs.
Tolerance of VDDQ
Since the OCDDQ pin is also used for detecting the 5VATX power supply, the upper threshold of the 5VATX UVLO is set to 1.25 V. Therefore, RL1 must be selected in such a way that the voltage at the OCDDQ pin must be higher than this threshold to avoid false triggering of the UVLO. In S3 mode, this over-current protection feature is disabled.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 2.
VTT Active Terminator
Both the tolerance of VFBDDQ and the ratio of external resistor divider R2/R1 impact the precision of VDDQ. When the control loop is in regulation, VDDQ = VFBQ x (1 + R2/R1). With a worst case (for all valid operating conditions) VFBDDQ tolerance of 2.0%, a worst case range of 2.5% for VDDQ can be assured if the ratio R2/R1 is specified as 1.10 1%.
Fault Protection of VDDQ Regulator
The VTT active terminator is a two quadrant linear regulator with two internal NFETs to provide current sink and source capability up to 1.8 A. It is active only when the VDDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While the VTT output is directly connected to the FBVTT pin, the VTT voltage is designed to automatically track at the half of the DDQ_REF voltage. This VTT voltage can be adjusted by using an external resistor divider in the feedback loop. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1 mW to 400 mW.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, a bi-directional current limit set to 2.4 A is implemented. This current limit is also used as a constant current source during VTT startup.
Dual Linear Regulators
In S0 mode, an external resistor (RL1) connecting the 5VATX supply to the OCDDQ pin sets the current limit for the high-side switch. An internal 40 mA current sink at the OCDDQ pin establishes a voltage drop across this resistor. The inductor node voltage is sensed at the SWDDQ pin through a resistor (RSWDDQ). The voltage at the OCDDQ pin is compared to the voltage at the SWDDQ pin when the high-side FET is turned on after a fixed period of blanking time thus avoiding false current limit triggering. If the voltage at SW_DDQ is lower than that at OCDDQ, an over-current condition occurs, during which, all regulators are latched off to protect against over-current. The IC can be powered up again only if any one of supply voltages (5VDUAL, 12VATX or 5VATX) is recycled or the SS pin is discharged to ground externally.
The dual linear regulators are formed by two high-gain controllers driving external NFETs. They are activated after the DDQ regulator is in regulation in S0 mode. The output voltage of each regulator is fed back through an external resistor divider. The feedback voltage is compared to an internal reference voltage VREF2 (=0.800 V) to achieve voltage regulation. Both linear regulators use a common soft-start ramp voltage set to 1.5 ms. Once they are activated, hiccup mode is employed during the soft-start period to protect them against short circuit or power failure conditions. In the soft-start interval, the feedback voltages of both regulators are compared with the soft-start ramping voltage. If either one of feedback voltages is 100 mV below the SS ramping voltage, a short circuit or power failure condition is detected,
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causing both regulators to be reset and initiate the soft start sequence again, as depicted in Figure 3. This hiccup mode feature is disabled once after both outputs are in regulation.
3.3VATX
reduce the internal power consumption as well as to avoid soft-start issues.
Fault Protection of Dual Linear Regulators
Internal soft-start is built-in to limit the in-rush current.
BOOT Pin Supply Voltage
_INREGDDQ
DRV_1P5
In a typical application, a flying capacitor is connected between the inductor LX node and the BOOT pin. In S0 mode, the 12VATX supply is tied to the BOOT pin through a Schottky diode. A 13 V zener diode must be put as close to the BOOT pin as possible to clamp the boot strapping voltage produced by the flying capacitor. In S3 mode the 12VATX supply is collapsed. The BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins and the flying capacitor.
Thermal Consideration
V1P5
V1P5 Loading
Figure 3. Hiccup Mode Soft-start of Dual Linear Regulators
Assuming an ambient temperature of 50C, the maximum allowed dissipated power of the QFN-20 package is 1.45 W. Thus a maximum of 0.8 A of DC current can be handled by the VTT regulator in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact.
Thermal Shutdown
These two linear regulators can be cascaded to generate the 1.5 V MCH core voltage with 2.4 V as the intermediate voltage. By using the 3.3 V ATX as the power supply for the external NFETs, up to 7 A can be delivered. If only one linear regulator is used, it is recommended to pull the feedback pin of the unused regulator to 5VDUAL to
The device will enter S5 mode from any operating mode if the junction temperature of the NCP5209 exceeds 140C. It will resume normal operation (from S5 to S0 mode) when the junction temperature falls below 115C.
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Power Up and Power Down Timing
5VSTBY or 5VDUAL 12 V 5V BUF_CUT PWRGD DDQ-S0 VTT Dual Lin
State
1
2
3
4
5
6
7
8
9 10
11
12 13 14 15
16
17 18
19
SO
S3
SO
S5
1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
5VSTBY or 5VSTB is ultimate chip enable. This supply has to be up first to ensure gates are in known state. 12 V and 5 V Supplies can Ramp in Either Order PWRGD asserts to indicate 5VDUAL has switched to 5VCC DDQ ramps up with timing set by the SS pin MCH and VTT both ramp once DDQ SS is completed and DDQ is within 90% of regulated voltage SO Operation Prepare S3 Mode -- BUF_CUT = H VTT and MCH will be turned off 12V and 5V ramp down to 0 volts, so as PWRGD Standard S3 State 12V and 5V ramp back to regulation PWRGD PWRGD ramps up to indicate that 5VDUAL has switched to 5VCC DDQ switches back to 250kHz and MCH ramps up VTT ramps up after BUF_CUT goes LOW SO Operation S5 mode -- BUF_CUT = L and (12VUVLO = L or 5VUVLO = L ) DDQ, VTT and MCH turned off S5 Mode
5VDUAL
OCDDQ
Figure 4. Timing Diagram
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State Transition Diagram
S5
BUF_CUT=0 AND _BOOTGD=1 AND _OCDDQGD=1
BUF_CUT=0 AND (_BOOTGD=0 OR _OCDDQGD=0)
S0
BUF_CUT=0 AND _BOOTGD=1 AND _OCDDQGD=1
BUF_CUT=1
S3
NOTES: Note: 5VDUAL is assumed to be in good conditions in any mode. All possible state transitions are shown. All unspecified inputs do not cause any state change.
Figure 5. State Transition Diagram.
Applications Information In some systems, the switching of 5VDUAL from 5VSTBY to 5VATX or vice versa does not automatically occur during mode transitions. To avoid overloading the 5VSTBY supply, a PWRGD signal, which is asserted only when 5VDUAL has been switched over to 5VATX, is created. This PWRGD signal is then used for controlling one of the UVLOs of this device so that the device can only enter S0 after the 5VDUAL has been switched over to 5VATX.
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PACKAGE DIMENSIONS
[Package Designation] MN SUFFIX CASE 505-01 ISSUE A
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
PIN 1 LOCATION
E 0.15 C 0.15 C
0.10 C A2 0.08 C A1 A3
REF
A C
SEATING PLANE
DIM A A1 A2 A3 b D D2 E E2 e K L
D2
18 X
L
e
1 9
18 X
K
18 10 18 X b
E2
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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